According to certain approaches in conventional semiconductor processing, gates in embedded non-volatile memory (eNVM) cells and in logic cells may be formed from common polysilicon gate layers. Typically, such processing provides for the deposition of polysilicon gate layers and insulating layers over memory cell areas and logic cell areas. Such layers are then patterned and etched to form stacks of control gates overlying floating gates in memory cell areas and polysilicon access gates in logic cell areas. This approach involves process complexity as the access gate, floating gate and control gate need to be doped. Further, step height differences between the logic cells and memory cells cause contact landing issues. Thus, special processing may be needed for landing contacts on the access gates. Moreover, like most n+ polysilicon control gate/floating gate stacked memory devices, erase saturation level can be a performance issue. The approach used in conventional processing typically necessitates additional process steps, including for example seven to nine additional masks, that increase cost and decrease efficiency of the integration process.
Scaling of devices has suggested the use of replacement metal gate (RMG) techniques in the integrated formation of access gates in logic cells and select gates in memory cells. However, integration of RMG techniques with eNVM cells presents challenges. In certain approaches, applying RMG techniques to existing processes for forming eNVM cells has presented issues relating to gate height differences between logic gates and eNVM control gate/floating stacked gates. Such height differences are problematic for planarization processes used in RMG techniques. Also, high aspect ratios are encountered during the metal fill process of the RMG process. As a result, the devices are formed with metal gap fill problems.
Accordingly, it is desirable to provide simpler and more efficient eNVM and RMG compatible integration schemes and enabling methodology. Also, it is desirable to provide methods for fabricating devices in which differences in gate heights during RMG processing and high aspect ratio filling processes are avoided. Further, it is desirable to provide methods for fabricating devices in which floating gates and metal gates are formed before control gates are formed over the floating gates. Also, it is desirable to provide devices in which the width of the control gate is not limited to the width of the floating gate. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.